The present invention relates to high density devices. In particular, embodiments of the present invention provide a method for manufacturing and a structure for connecting conductors to multiple planes in a three-dimensional high density semiconductor device, such as memory device.
Three dimensional (3D) semiconductor devices are characterized by multiple layers. In a memory device, each of the layers can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells stacked in spaced-apart ridge-like structures. The active layers can be made from a doped (p-type or n-type) or undoped semiconductor material. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array.
Examples of memory devices like this are described in commonly owned U.S. Patent Publication No. 2012/0182806, filed Apr. 1, 2011, entitled Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures by inventors Shih-Hung Chen and Hang-Ting Lue and in commonly owned U.S. Pat. No. 8,363,476, filed 19 Jan. 2011, entitled Memory Device, Manufacturing Method And Operating Method Of The Same, by inventors Hang-Ting Lue and Shi-Hung Chen, both of which are incorporated by reference as if fully set forth herein. In these examples, the active strips in a set in each layer are coupled to a corresponding pad in a stack of pads. The pads provide landing areas for interlayer conductors, which are connected to overlying conductor lines as bit lines for the memory device. The interlayer conductors extend vertically through the stack of pads in the 3D device, and can require relatively large area in the layout to account for taper and alignment issues that arise in manufacture, particularly as the number of layers increases. The relatively large area required can become a limiting factor in the density of overlying interconnect lines, such as global bit lines.
The density of the interconnect lines can be critical to device performance and cost. For example, NAND memory can include page operations, including page read and program. The size of a page, and therefore data rate, in such devices depends on the global bit line density. To achieve a higher bit line density and therefore a faster memory device, pitch of the bit lines needs to be reduced (where the pitch is the average center to center distance between adjacent features like the bit lines).
It is desirable, therefore, to provide a method and structure for making interconnects, such as high density bit lines, which make contact to a plurality of layers in a 3D device.